Projects per year
Abstract
ULTRARAM™ is a III-V semiconductor memory technology which exploits resonant tunneling to allow ultra-low-energy memory logic switching (per unit area), whilst retaining non-volatility. Single-cell memories developed on GaAs substrates with a revised design and atomic-layer-deposition Al 2 O 3 gate dielectric demonstrate significant improvements compared to prior prototypes. Floating-gate (FG) memories with 20-μm gate length show 0/1 state contrast from 2.5-V program-read-erase-read (P/E) cycles with 500-μs pulse duration, which would scale to sub-ns switching speed at 20-nm node. Nonvolatility is confirmed by memory retention tests of 4×10 3 s with both 0 and 1 states completely invariant. Single cells demonstrate promising endurance results, undergoing 10 4 cycles without degradation. P/E cycling and disturbance tests are performed using half-voltages (±1.25 V), validating the high-density random access memory (RAM) architecture proposed previously. Finally, memory logic is retained after an equivalent of >10 5 P/E disturbances.
| Original language | English |
|---|---|
| Title of host publication | 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) |
| Publisher | IEEE |
| Pages | 1-3 |
| Number of pages | 3 |
| ISBN (Electronic) | 9781728181769 |
| ISBN (Print) | 9781728181776 |
| DOIs | |
| Publication status | Published - 12/05/2021 |
Projects
- 3 Finished
-
MSI: Continuation Study of Compound Semiconductor Non-volatile RAM Manufacture on Si Substrates
Hayne, M. (Principal Investigator)
Engineering and Physical Sciences Research Council
1/10/19 → 30/06/22
Project: Research
-
MSI: H2020: Ultra-low-power NVRAM for Internet-of-Things Sensors
Hayne, M. (Principal Investigator)
20/05/19 → 31/10/20
Project: Research
-
Ultra-low energy, non-volatile, random access memory
Hayne, M. (Principal Investigator)
The Joy Welch Charitable Trust
4/04/18 → 30/04/19
Project: Research
-
ULTRARAM: toward the development of a III-V semiconductor, non-volatile, random-access memory
Lane, D., Hodgson, P., Potter, R., Beanland, R. & Hayne, M., 31/05/2021, In: IEEE Transactions on Electron Devices. 68, 5, p. 2271-2274 4 p.Research output: Contribution to Journal/Magazine › Journal article › peer-review
Open AccessFile2 Citations (Scopus)167 Downloads (Pure) -
ULTRARAM™: Design, Modelling, Fabrication and Testing of Ultra-low-power III-V Memory Devices and Arrays
Lane, D., 2021, Lancaster University. 221 p.Research output: Thesis › Doctoral Thesis
Open AccessFile128 Downloads (Pure)